In microelectronics packaging, there is a continuing effort to produce smaller and faster electronics. 3D packaging architectures, including stacked die architectures, may offer several advantages (such as smaller size and reduced interconnect distances) over 2D packaging architectures.
Typical 2D packaging architectures may include a die flip-chip connected to a substrate, such that the active surface (including devices and metal layers) of the die faces the substrate. A cooling solution may then be provided on the exposed backside of the die. The cooling solution may include a heat sink, an integrated heat spreader, or a fan, for example.
FIG. 1 illustrates a typical 3D package 100 including a substrate 110, a central processing unit (CPU) die 120, dynamic random access memory (DRAM) die 130, a flash memory die 140, and an analog die 150. Substrate 110 may typically include a printed circuit board or motherboard. For 3D package 100 to function, the active surface of each component must be electrically connected to substrate 110 or the active surface of an adjacent component. To interconnect the active surfaces, conductive through silicon vias (TSV) 160 may be extended through the components.
For example, CPU die 120 may be flip-chip connected to substrate 110 such that the active surface of CPU die 120 faces substrate 110. DRAM die 130 may be connected to CPU die 120 with bump soldering such that the active surface of DRAM die 130 faces the inactive surface of CPU die 120. The TSV of CPU die 120 may then electrically connect the active surface of DRAM die 130 to the active surface of CPU die 120 or to substrate 110.
In a similar manner, the active surfaces of each component may be electrically interconnected.